The present invention relates to a data processor of high performance, and more particularly, it relates to a data processor performing condition execution on the basis of a flag on which an operation result is reflected.
In a data processor, pipeline processing is frequently employed for improving the performance. As one of large factors hindering performance improvement in the pipeline processing, there is overhead resulting from execution of a branch. While various contrivances are made as to this, there is condition execution of an instruction as one thereof.
ARM (VLSI Technology), which is a 32-bit RISC processor, provides an execution condition specify field of four bits for instruction codes of all instructions, and can condition-execute all instructions. When executing one instruction only when a certain condition is satisfied, for example, it can be processed without causing a branch. When performing unconditional execution, one bit pattern of this field of four bits specifies regular execution.
Thus, some processors such as ARM reduce penalty of a branch by rendering many instructions condition-executable, for attaining performance improvement and reduction of power consumption. When making setting to perform condition execution in all instructions, however, fields specifying execution conditions are required for all instructions and hence the instruction length lengthens.
Particularly when ROMing and storing a program to be built in, reduction of the code size becomes important. When forcibly excessively suppressing the instruction length for reduction of the code size, an area describing actual instructions further reduces by the execution condition specify fields, and hence the number of encodable instructions reduces. Thus, when comprising condition specify fields for all instructions, there has been such a problem that the code size enlarges.
TMS320C54x series (TI), which is a 16-bit fixed-point DSP, comprises an XC instruction specifying execution of a next instruction (or subsequent two instructions) only when a condition is satisfied thereby reducing penalty of a branch. This technique requires one clock cycle for specifying the execution condition, and hence has a small effect. Further, there have been such problems that it is difficult to implement sophisticated parallel processing of a superscalar, VLIW and the like used in the processor, while an external interrupt immediately after the XC instruction is also limited.
In many data processors, an operation result or a comparison result is held as a flag in a processor status word, and this flag can be referred to as an execution condition for a condition branch instruction or a condition trap instruction. In this flag, information of a single operation result or comparison result is generally held. However, it is useful for reduction of code efficiency and reduction of penalty by a branch if a combination of a plurality of operation results or an operation result other than an immediately precedent operation can be referred to as the condition. Further, the number of registers used as those for working is also reducible.
For example, the processor Power PC (IBM) comprises a condition register consisting of eight flag groups consisting of 4-bit flags, and is contrived to be capable of specifying to which flag group to reflect the operation result in a comparison instruction and to be capable of referring to an arbitrary flag in a condition branch instruction or the like. A logical operation between the flags is also possible. However, fields for specifying a flag group storing the comparison result in the comparison instruction and the flag referred to in determination of the branch condition in the condition branch instruction are required and the instruction length lengthens by the field area. There has been such a problem that, when forcibly suppressing the instruction length, the number of instructions encodable to short instructions reduces and the code size enlarges similarly to the processor ARM.
In order to efficiently handle Boolean algebra, some processors comprise an instruction setting xe2x80x9c1xe2x80x9d when the condition is true or xe2x80x9c0xe2x80x9d when false. For example, the processor x86 series (Intel) comprises a SETcc instruction. However, there has been such another problem that, only one condition can be determined with these instructions and hence complex expressions cannot be efficiently processed when a composite condition of a plurality of condition is specified or the like.
The present invention has been proposed in order to solve the aforementioned problems, and aims at obtaining a high-performance data processor having excellent code efficiency, which can reduce penalty of a branch by condition execution.
It aims at obtaining a high-performance data processor implementing condition execution with an instruction set having a small instruction code size, which can reduce penalty of a branch.
A first aspect of the data processor according to the present invention is an apparatus receiving a parallel processing instruction including first and second instruction codes defining first and second instructions, which comprises a first decoder for decoding the first instruction code to output a first decoded result, a second decoder for decoding the second instruction code to output a second decoded result, flag information storage means for storing flag information, first execution control means for controlling execution of the first instruction on the basis of the first decoded result, second execution control means for controlling execution of the second instruction on the basis of the second decoded result and first execution condition judgment means for outputting second instruction execution control information which controls whether to permit or inhibit the execution of the second instruction to the second instruction execution control means on the basis of whether or not the flag information satisfies a second instruction execution condition when the first instruction is an execution condition specifying instruction defining an execution condition for the second instruction based on the flag information, and the second execution control means controls whether to permit or inhibit the execution of the second instruction on the basis of indication of the second instruction execution control information.
As in a second aspect of the data processor, it may further comprise second execution condition judgment means for outputting first instruction execution control information which controls whether to permit or inhibit the execution of the first instruction to the first execution control means on the basis of whether or not the flag information satisfies a first instruction execution condition when the second instruction is an execution condition specifying instruction defining an execution condition for the first instruction based on the flag information, and the first execution control means may control whether to permit or inhibit the execution of the first instruction on the basis of indication of the first instruction execution control information.
As in a third aspect of the data processor, the parallel processing instruction may further comprise third and fourth instruction codes defining third and fourth instructions, it may further include a third decoder for decoding the third instruction code to output a third decoded result; a fourth decoder for decoding the fourth instruction code to output a fourth decoded result; third execution control means for controlling execution of the third instruction on the basis of the third decoded result; fourth execution control means for controlling execution of the fourth instruction on the basis of the fourth decoded result; and third execution condition judgment means for outputting fourth instruction execution control information which controls whether to permit or inhibit the execution of the fourth instruction to the fourth execution control means on the basis of whether or not the flag information satisfies a fourth instruction execution condition when the third instruction is an execution condition specifying instruction defining an execution condition for the fourth instruction based on the flag information, wherein the fourth execution control means may control whether to permit or inhibit the execution of the fourth instruction on the basis of indication of the fourth instruction execution control information.
As in a fourth aspect of the data processor, the parallel processing instruction may further include a third instruction code defining a third instruction, it may further comprise a third decoder for decoding the third instruction code to output a third decoded result and third execution control means for controlling execution of the third instruction on the basis of the third decoded result, wherein the first execution condition judgment means may output third instruction execution control information which controls whether to permit or inhibit the execution of the third instruction to the third execution control means on the basis of whether or not the flag information satisfies a third instruction execution condition when the first instruction is the execution condition specifying instruction also defining an execution condition for the third instruction based on the flag information as well as the execution condition for the second instruction, and the third execution control means may control whether to permit or inhibit the execution of the third instruction on the basis of indication of the third instruction execution control information.
As in a fifth aspect of the data processor, the second instruction execution condition and the third instruction execution condition may be independently described in the first instruction code respectively when the first instruction is the execution condition specifying instruction.
As in a sixth aspect of the data processor, the second instruction execution condition and the third instruction execution condition may be partially duplicated in the first instruction code when the first instruction is the execution condition specifying instruction, the second instruction execution condition may consist of a common execution condition and an execution condition specific to the second instruction, and the third instruction execution condition may consist of the common execution condition and an execution condition specific to the third instruction.
As in a seventh aspect of the data processor, a common execution condition common to the second instruction execution condition and the third instruction execution condition may be described in the first instruction code when the first instruction is the execution condition specifying instruction, and the first execution condition judgment means may output the second instruction execution control information indicating permission of the execution of the second instruction while outputting the third instruction execution control information indicating inhibition of the execution of the third instruction when satisfying the common executing condition, and may output the second instruction execution control information indicating inhibition of the execution of the second instruction while outputting the third instruction execution control information indicating permission of the execution of the third instruction when not satisfying the common execution condition.
As in an eighth aspect of the data processor, the flag information may include first and second flag information, and the execution condition specifying instruction may be an instruction specifying an execution condition consisting of a composite condition decided by the first flag information and the second flag information.
A ninth aspect of the data processor according to the present invention is an apparatus capable of executing an instruction at least including a flag update instruction to update flag information and a flag control execution instruction whose execution content is decided on the basis of the flag information, which comprises flag information storage means for storing the flag information and instruction execution control means for outputting flag update relevant information relevant to flag updating to the flag information storage means on the basis of the flag update instruction when an instruction to be executed is the flag update instruction and for execution-controlling the flag control execution instruction with an execution content decided on the basis of the content of the flag information when the instruction is the flag control execution instruction, the flag information includes first and second flag information each including information of at least one flag, and the flag information storage means may store the first flag information as the second flag information and update the first flag information on the basis of the flag update relevant information.
As in a tenth aspect of the data processor, the first flag information may include information of a plurality of flags, and the second flag information may include information of a plurality of flags.
As in an eleventh aspect of the data processor, the flag information may further include third flag information, and the flag information storage means may store the second flag information as the third flag information when the second flag information is updated.
A twelfth aspect of the data processor according to the present invention is an apparatus capable of executing an instruction at least including a flag update instruction to update flag information and a flag control execution instruction whose execution content is decided on the basis of the flag information, which comprises flag information storage means for storing the flag information and instruction execution control means for outputting flag update relevant information relevant to flag updating to the flag information storage means on the basis of the flag update instruction when an instruction to be executed is the flag update instruction and for execution-controlling the flag control execution instruction with an execution content decided on the basis of the flag information when the instruction is the flag control execution instruction, the flag information includes first and second flag information each including information of at least one flag and update flag information specifying flag information to be updated in the first and second flag information, and the flag information storage means updates one of the first and second flag informations indicated by the update flag information on the basis of the flag update relevant information.
As in a thirteenth aspect of the data processor, the first flag information may include information of a plurality of flags, and the second flag information may include information of a plurality of flags.
As in a fourteenth aspect of the data processor, the flag control execution instruction may include an instruction whose execution content is decided on the basis of only the second flag information.
As in a fifteenth aspect of the data processor, the flag control execution instruction may include an instruction whose execution content is decided on the basis of a composite condition combining the first flag information and the second flag information.
A sixteenth aspect of the data processor according to the present invention is an apparatus capable of executing an instruction at least including a flag control execution instruction whose execution content is decided on the basis of flag information, which comprises flag information storage means for storing the flag information and instruction execution control means for execution-controlling the flag control execution instruction whose execution content is decided on the basis of the content of the flag information when the instruction is the flag control execution instruction, the flag information includes first and second flag information each including information of at least one flag, and the flag control execution instruction includes an instruction writing a first value in a prescribed storage unit on the basis of a composite condition decided by the first and second flag information when the composite condition is satisfied while writing a second value in the prescribed storage unit when not satisfied.
As in a seventeenth aspect of the data processor, the first flag information may include information of a plurality of flags, and the second flag information may include information of a plurality of flags.
As in an eighteenth aspect of the data processor, the prescribed storage unit may include at least one of a register, an accumulator and a memory.
In the first aspect of the data processor according to the present invention, the first execution condition judgment means outputs the second instruction execution control information which controls whether to permit or inhibit the execution of the second instruction to the second execution control means on the basis of whether or not the flag information satisfies the second instruction execution condition when the first instruction is the execution condition specifying instruction defining an execution condition for the second instruction based on the flag information, and the second execution control means controls whether to permit or inhibit the execution of the second instruction on the basis of indication of the second instruction execution control information.
When the first instruction is the execution condition specifying instruction, therefore, various execution conditions for the second instruction can be set while fully utilizing the first instruction code by describing the execution condition for the second instruction in the first instruction code, whereby processing employing a branch instruction can be decreased by this and reduction of branch penalty can be attained.
When the first instruction is the execution condition specifying instruction, further, the code size of the second instruction code can be reduced since it is not necessary to describe the execution condition for the second instruction in the second instruction code. Consequently, reduction of the cost can be attained following reduction of a program capacity created employing an instruction executable in this data processor.
In addition, prescribed processing can be efficiently executed by setting various execution conditions for the second instruction with the first instruction as the execution condition specifying instruction, whereby reduction of power consumption can be attained by reducing the number of clock cycles of the data processor necessary for implementation.
In the second aspect of the data processor, the second execution condition judgment means outputs the first instruction execution control information indicating whether to permit or inhibit the execution of the first instruction to the first execution control means on the basis of whether or not the flag information satisfies the first instruction execution condition when the second instruction is the execution condition specifying instruction defining an execution condition for the first instruction based on the flag information, and the first execution control means controls whether to permit or inhibit the execution of the first instruction on the basis of indication of the first instruction execution control information.
Also when the second instruction is the execution condition specifying instruction, therefore, various execution conditions for the first instruction can be set while fully utilizing the second instruction code by describing the execution condition for the first instruction in the second instruction code, and reduction of the branch penalty, reduction of the cost and reduction of power consumption can be attained beyond the first aspect.
In the third aspect of the data processor, the third execution condition judgment means outputs the fourth instruction execution control information indicating whether to permit or inhibit the execution of the fourth instruction on the basis of whether or not the flag information satisfies the fourth instruction execution condition when the third instruction is the execution condition specifying instruction defining the fourth instruction execution condition based on the flag information, and the fourth execution control means controls whether to permit or inhibit the execution of the fourth instruction on the basis of indication of the fourth instruction execution control information.
When the third instruction is the execution condition specifying instruction, therefore, various execution conditions for the fourth instruction can be set while fully utilizing the third instruction code by describing the execution condition for the fourth instruction in the third instruction code, whereby reduction of the branch penalty, reduction of the cost and reduction of power consumption can be attained beyond the first and second aspects.
In the fourth aspect of the data processor, the first execution control means outputs the third instruction execution control information indicating whether to permit or inhibit the execution of the third instruction to the third execution control means on the basis of whether or not the flag information satisfies the third instruction execution condition when the first instruction is the execution condition specifying instruction also defining an execution condition for the third instruction based on the flag information as well as the execution condition for the second instruction, and the third execution control means controls whether to permit or inhibit the execution of the third instruction on the basis of indication of the third instruction execution control information.
Consequently, the fourth aspect of the data processor can control execution and inhibition of two instructions (second and third instructions) by one execution condition specifying instruction (first instruction), whereby effective execution condition specification can be performed.
In the fifth aspect of the data processor, the second instruction execution condition and the third instruction execution condition are independently described in the first instruction code respectively, whereby the second and third instruction execution conditions can be inherently set.
In the sixth aspect of the data processor, the second instruction execution condition and the third instruction execution condition are partially duplicated in the first instruction code when the first instruction is the execution condition specifying instruction, whereby the second and third instruction execution conditions can be inherently set while effectively utilizing the first instruction code.
In the seventh aspect of the data processor, the first execution condition judgment means outputs the second instruction execution control information indicating permission of the execution of the second instruction while outputting the third instruction execution control information indicating inhibition of the execution of the third instruction when satisfying the common execution condition and outputs the second instruction execution control information indicating inhibition of the execution of the second instruction while outputting the third instruction execution control information indicating permission of the execution of the third instruction when not satisfying the common execution condition, whereby a series of processing accompanied by a condition branch instruction can be batch-performed on the basis of the determination of the first execution condition judgment means.
In the eighth aspect of the data processor, the first flag information includes the first and second information and the execution condition specifying instruction is the instruction specifying the execution condition consisting of the composite condition decided by the first flag information and the second flag information, whereby an execution condition consisting of a complex composite condition can be specified.
The flag information storage means in the ninth aspect of the data processor according to the present invention stores the first flag information as the second flag information and updates the first flag information on the basis of the flag update relevant information, whereby updating of the second flag information is also performed at the same time when updating of the first flag information is performed.
Therefore, the first and second flag information can be updated by simply supplying the flag update relevant information to the flag information storage means without specifying the flag information to be updated in the flag update instruction.
Consequently, the code size of the instruction code for the flag update instruction can be reduced since a specify area for the flag information to be updated can be omitted in relation to the first and second flag information, whereby the first and second flag information can be updated with a flag update instruction having a small code size.
In the tenth aspect of the data processor, the first flag information includes the information of the plurality of flags and the second flag information includes the information of the plurality of flags, whereby the information of the plurality of flags in the first and second flag information can be batch-updated respectively by simply supplying single flag update relevant information to the flag information storage means.
In the eleventh aspect of the data processor, the flag information storage means stores the second flag information as the third flag information when the second flag information is updated, whereby the first to third flag information can be updated by simply supplying the flag update relevant information to the flag information storage means without specifying the flag information to be updated in the flag update instruction.
Consequently, the code size of the instruction code for the flag update instruction can be reduced since the specify area for the flag information to be updated can be omitted in relation to the first to third flag information, whereby the first to third flag information can be updated with a flag update instruction having a small code size.
In the twelfth aspect of the data processor, the flag information includes the first and second flag information and information of a flag specify flag specifying the flag information to be updated in the first and second flag information, and the flag information storage means updates one of the first and second flag informations indicated by the update flag information on the basis of the flag update relevant information.
Therefore, the flag information to be updated can be intentionally decided by properly setting the updated flag information without providing information specifying the flag information to be updated in the flag update instruction.
In the thirteenth aspect of the data processor, the first flag information includes the information of the plurality of flags and the second flag information includes the information of the plurality of flags, whereby the information of the plurality of flags indicated by the updated flag information can be updated in the first and second flag information by simply supplying single flag update relevant information to the flag information storage means.
In the fourteenth aspect of the data processor, the flag control execution instruction includes the instruction whose execution content is decided on the basis of only the second flag information, and execution control of an instruction based on a specific condition employing only the second flag information is enabled.
In the fifteenth aspect of the data processor, the flag control execution instruction includes the instruction whose execution content is decided on the basis of the composite condition combining the first flag information and the second flag information, whereby execution control of an instruction based on a complex composite condition is enabled.
In the sixteenth aspect of the data processor, the flag control execution instruction includes the instruction writing the first value in the prescribed storage unit when the composite condition is satisfied and writing the second value when not satisfied on the basis of the composite condition decided by the first and second flag information, whereby a sophisticated write instruction can be executed.
In the seventeenth aspect of the data processor, the first flag information includes the information of the plurality of flags and the second flag information includes the information of the plurality of flags, whereby a more sophisticated write instruction further complexing the aforementioned composite condition can be executed.
In the eighteenth aspect of the data processor, the prescribed storage unit includes at least one of the register, the accumulator and the memory, whereby a sophisticated write instruction for the accumulator or the memory can be executed.